Semiconductor memory testers are roughly divided into a memory testing apparatus of the type testing semiconductor memories in wafer form prior to packaging and a memory testing apparatus of the type testing semiconductor memories in packaged form. The memory testing apparatus of the type that tests semiconductor memories (hereinafter referred to simply as memories) prior to packaging greatly differs from the memory testing apparatus of the type testing packaged memories in the possession of the function that decides whether a failing cell is recoverable and, if so, recovers the failing cell.
In FIG. 1 there is depicted the general outline of the functional configuration of a memory testing apparatus equipped with the failure recovery function. The memory testing apparatus, denoted generally by 100, comprises: a main controller 111, a pattern generator 112; a timing generator 113; a waveform formatter 114; a logic comparator 115; a group of drivers 116; a group of analog comparators 117; a failure analysis memory 118; a failure recovery analysis processing unit 119; a logical-amplitude reference voltage source 121; a comparison reference voltage source 122; and a device power supply 123. The main controller 111, the pattern generator 112, the timing generator 113, the waveform formatter 114, the logic comparator 115 and the failure analysis memory 118 are connected to a tester bus 124.
The main controller 111 is usually constituted by a computer, which executes a user's prepared test program to control mainly the pattern generator 112 and the timing generator 113, by which test pattern data, that is, address data, a control signal and expected value data, is generated by the pattern generator 112, then the test pattern data except the expected value data is converted by the waveform formatter 114 to a test pattern signal having a real waveform, and the test pattern signal is voltage amplified by the driver 116 to a signal of a waveform having an amplitude set in the logical- amplitude reference voltage source 121, thereafter being applied to a memory under test 200 formed on a semiconductor wafer WH to store therein the test data,
A response signal read out of the memory under test 200 is applied to the analog comparator 117 which compares it with a reference voltage provided from the comparison reference voltage source 122 to decide whether it has a predetermined logical level (H-logic voltage, L-logic level), and the signal decided to have the predetermined logical level is compared by the logic comparator 115 with the expected value data fed from the pattern generator 112; when a mismatch with the expected value data is found, it is decided that a memory cell of the address from which the response signal was read out is failing, then fail data from the logic comparator 115 is stored in the address position of the failure analysis memory 118 corresponding to that readout address, and at the conclusion of the test it is decided by the failure recovery analysis processing unit 119 whether the failing cell is recoverable or not. In FIG. 1 there is shown the case where the write data and the read data of the memory 200 are both one-bit, but when these pieces of data are composed of plural bits, the numbers of drivers 116 and analog comparators 117 used are the same as the number of bits.
With reference to FIG. 2 conceptually showing the redundant memory 200, a brief description will be given below of its internal configuration in which the number N of data bits is plural and spare lines are provided accordingly.
In memory cell array groups which are so-called memory planes 201-0, 201-1, 201-2, - - - , 201-N-1 are respectively stored zeroth bit data bit-0, first bit data bit-1, . . . , N-th bit data bit-N of N-bit data. In the respective memory cell array groups (memory planes) 201-0, 201-1, 201-2, - - - there are formed a plurality of memory arrays 202, and a spare cell line 203 is formed adjacent the position where the respective memory cell arrays each are formed. The spare cell line is commonly called a spare line, which is formed by an arrangement of memory cells of the same number as that of the memory cells on each address line in the memory cell array 202; for example, two or more memory cells are formed in each of a column address direction COL and a row address direction ROW.
The failure analysis memory 118 comprises, as depicted in FIG. 3: a storage part AFM; a multiplexer MUX which selectively applies an address signal to an address terminal An of the storage part AFM; and an address converter ACN which converts an address signal in the test pattern data fed from the pattern generator 112 (see FIG. 1) to an address signal of the corresponding address signal of the failure analysis memory 118; upon each detection of a mismatch in the logic comparator 115, a write signal WRITE is applied to a write control terminal WE of the storage part AFM in synchronization with the corresponding fail detection signal. Fail data, which is the output from the logic comparator 115, is provided to a data terminal Dn of the storage part AFM.
The addresses of the memory under test 200 have a one-to-one correspondence to the addresses of the storage AFM; if exactly identical, the address signal applied to the address converter ACN passes therethrough intact.
The failure recovery analysis processing unit 119 comprises, as shown in FIG. 4, a control part 10 and a recovery analysis unit 20 which is controlled by the control part 10 to operate. The recovery analysis unit 20 comprises a bit designating part 21, a latch circuit 22, processing part 23, and an address generator 24.
During testing the memory 200, in the failure analysis memory 118 the multiplexer MUX selects the address signal fed to its input terminal B from the address converter ACN and provides it to the address input terminal An of the storage part AFM, and upon each occurrence of a mismatch in the logic comparator 115, fail data from the logic comparator 115 is stored in that address of the storage part AFM corresponding to the address of the memory under test 200 for which the mismatch is detected. Incidentally, each cell of the storage part AFM is pre-initialized to the “0” logic.
The fail data mentioned herein is data which has a bit of the “1” logic for which a mismatch was found in the result of comparison between the data read out of the memory under test 200 and the expected value data and a bit of the “0” logic for which no such a mismatch was detected.
During the failure recovery analysis the multiplexer MUX selects address signals applied to its input terminal An from the address generator 24 (FIG. 4) in the failure recovery analysis processing unit 119 and provides the selected address signals to the address terminal An of the storage part AFM, and the pieces of fail data are read out of the storage part AFM one after another.
The N-bit fail data thus read out of the storage part AFM is provided to the bit designating part 21 (FIG. 4) in the failure recovery analysis processing unit 119. In the bit designating part 21, data of the bit in the fail data designated by the output from a bit designating register 21A is fed via an OR circuit 21C to the latch circuit 22. That is, logarithmic value data of a counter 10F in the control part 10 is provided to the bit designating register 21A, then the bit designating register 21A decodes the count value data, and the output from the bit designating register 21A enables any one of gates 21B-0, . . . , 21B-N-1 provided corresponding to respective bits in the N-bit fail data, through which the corresponding bit in the fail data is provided to the latch circuit 22.
The one-bit data thus provided to the latch circuit 22 is recognized by the address signal from the address generator 24 as to form which address was read out the fail data to which the one-bit data belongs, and furthermore, which bit in the fail data read out of that address is failing, that is, the position on the cell line (called an address line) designated by an address on the memory cell array, is specified by the content (bit designating data) of the bit designating register 21A. The processing part 23: reads thereinto, upon each latching of a “1” into the latch circuit 22, the corresponding address and bit designating data; specifies the address and bit position of the fail data; counts the number of failing cells at the specified bit position (memory plane) for each address line; upon conclusion of the readout from all addresses, analyzes whether the address line is recoverable with the spare line 203 formed adjacent each memory cell array; and, if recoverable, the address line concerned is electrically replaced with the corresponding spare line. Next, the counter 10F is incremented by one, then fail data of all addresses in the storage part AFM is read out therefrom, then for the next bit number (on the next memory plane) of the fail data, the number of failing cells for each address line is counted, and the address line, if recoverable, is replaced with the corresponding spare line 203. Thereafter, the same recovery analysis processing as mentioned above is performed for each bit number of the fail data. In this way, a defective memory can be changed to a non-defective memory.
As described above, in the prior art the fail data of the bit designated by the bit designating part 21 is sent to the processing part 23 bit by bit in address order. That is, the recovery analysis processing, in which the memory cell array groups 201-0, 201-1, 201-2, . . . shown in FIG. 2 are designated by the bit designating register 21A on a group-wise basis and all the addresses of each memory cell array group are read out, is carried out for each of the memory array cell groups 201-0, 201-1, 201-2, . . . Accordingly, the prior art method is defective in that much time is required for the recovery analysis.
An object of the present invention is to provide a memory recovery analysis method that enables a recovery analysis to be made in a shorter time than in the prior art, and a memory testing apparatus using the recovery method.